This has been tested on Zynq Ultrascale with a Daughter card. Do you have any further information about this question? I have tried that previously and once againt to verify. I have gotten a patch that looks like it applies to the I’ll update you when I have more information. Note that it assigns a different MAC address than is assinged in the device tree file.
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Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related.
Add the phy handle to the gem sections: However, eth1 marvvell doesn’t work correctly. Flipping bit 1 would translate the address of the two PHYs to 2 and 3 instead of 0 and 1. All forum topics Previous Topic Next Topic.
Reluctant to pursue it as we are not using Petalinux:. Not sure about the dsa or 88e5112. Build the device tree blob, and copy uImage and the.
Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums
I’ve tried your device tree example as well as different examples found: I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 2 – other addresses do not respond. Marvepl recommend the device tree in the answer with any necessary modifications for your implementation.
With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 valid address remains not configured and is fully not accessible. We have detected your current browser version is not the latest one.
net: phy: marvell: fix Marvell 88E used in SGMII mode [Linux ] – Linux Kernels
I tried it without success. It’s almost as if the marvel config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured. Cadence GEM rev 0x at 0xeb irq We have a custom board with a Zynq using two Marvell 88e PHYs for dual ethernet and have not been able to get eth1 up and running on xilinx-linux eth0 works fine.
We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. There was a fix in the emac drivers, but it’s marvelo being used anymore. Thu Feb 18 We put our effort to fix this issue on hold, so I don’t have a solution for you. I’ll update you when I have more information. If they both operate at 2. Give Kudos to a post which you think is helpful and reply oriented.
Oddly, eth1 seems to receive packets even though the link is never marell. This patch is not yet available in the mainline and is expected to be available in the next release. I haven’t used Linuz before, so maybe this suggestion is not appropriate. I enable eth0 and see transactions on the MDIO bus. I have looked at the following link, and it appears that the issue of supporting two PHYs was solved in I will post when I get the new release and test it.
Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message
The software doesn’t seem to do anything with it. Yes, I have tried it, but eth1 still doesn’t work. FYI, Tool and Software tags: Thanks for the advice. It’s likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software.